The use of embedded memories has become increasingly common in the design of integrated circuits such as microprocessors. A 2T (e.g., two-transistor) gain cell is one type of embedded memory which is commonly used in dynamic random access memory (DRAM). In a 2T cell there is typically one transistor to control read operations and one transistor to control write operations.
The amount of gate leakage current in a memory cell, such as a 2T gain cell, can determine how often a memory cell will need to be refreshed, and is often used as a measure of memory cell quality. When a memory cell is in the middle of a refresh cycle for example, devices such as a microprocessor that wish to access the memory cell are required to wait until the refresh process is complete, thereby impacting system performance.
In the past, the amount of leakage current existing in memory cells was negligible due to relatively thick oxide layers within the transistors of the memory cells. However, as oxide layers continue to become thinner and thinner due to technology scaling for example, the measure of leakage current within memory cell devices has become an increasingly important design limitation.